Calibre auto-waivers in DFM Checker: auto waiving un-relevant DFM hints to focus on the key ones - ST Microelectronics

DFM Checker is a solution developed at STMicroelectronics that leverages Calibre YieldAnalyzer and YieldEnhancer to drive designer into application of DFM guidelines, with goal to effectively increase layout design robustness wrt. known or suspected yield loss mechanisms or reliability issues, without increasing silicon area (and cost).

While running DFM Checker, for different reasons (e.g. to respect higher priority design constraints or to preserve external hard IPs) the designer may need to waive some of the DFM Checker results in order to focus on those relevant layout improvement hints that allow to achieve the expected DFM compliance for the IP block or the full chip.

Thanks to Calibre Auto-Waivers integration in the DFM flow, on the one hand designer can easily implement waiver management automatically during Calibre run without modifying the DFM Checker sources. On the other hand, it is possible to consistently take into consideration wavers in DFM score results and accurately track all the related information.

This methodology allows to shorten the DFM verification process while improving the level of application of DFM guidelines and eventually the design quality.

This talk will describe the benefits enabled by the integration of Calibre Auto-Waivers in the DFM Checker solution available for Bipolar-CMOS-DMOS (BCD) technologies. The presentation will also demonstrate the application on some real layout cases.