Assembly verification flow for silicon interposers

Silicon interposers continue to be the major driver for high end, 2.5D-IC systems. As the silicon interposer designs evolve over the years, foundries currently allow deep trench capacitors to be integrated (embedded) into the silicon interposer routing to improve signal and power integrity (SI/PI). The number of embedded capacitors in a silicon interposer design can exceed 50K instances. On the silicon interposer design level, the foundry provides the designer with different types of embedded capacitors cells that the designers need to instantiate all over the design to reduce any undesired SI/PI effects.

From a 2.5D-IC assembly verification perspective, capturing the intended connectivity of the dies, silicon interposer, embedded capacitors and organic package can be a challenge. A “system netlist” which crosses different design domains needs to be created to drive assembly level LVS. On the other hand, capturing the physical connections of all the embedded capacitors instances (based on their type) is crucial. Designers need to verify that all embedded capacitors ports are accurately connected to the correct power or ground nets. Eventually, designers need an assembly verification flow that enables LVS checking across dies, silicon interposer, embedded capacitors, and package substrate.

In this paper, Broadcom presents a fully automated, easy to use assembly verification flow that is based on Xpedition Substrate Integrator (xSI), Calibre DESIGNrev and Calibre 3DStack. The flow allows the user to generate a system source netlist that accounts for the embedded capacitors in silicon interposer designs, create the Calibre 3DStack runset automatically, run Calibre 3DStack to verify that the full 2.5D-IC physical assembly is LVS clean.