Extending design technology co-optimization from technology launch to HVM with Calibre Fab Solutions

As IC designs get larger and manufacturing processes get more complex, the semiconductor industry finds itself needing new solutions to prevent the propagation of systematic defects, streamline product cycle time and deliver high-quality, reliable chips. Traditionally, engineers have improved performance, power efficiency, density and cost through design-technology co-optimization (DTCO) techniques that bring end-product metrics to bear on design and technology choices.

However, these traditional approaches don't connect design and manufacturing data through the entire flow; there are still 'walls' between modules along the way that block the smooth feedback and feed forward of data. The result is that the traditional DTCO is no longer enough to ensure the design is free of the more frequently occurring systematic failures tied to complex design-process interactions.

In this paper, we introduce an extended DTCO platform called Calibre Fab Solutions with systematic information exchange and analytics overarching various design-to-manufacturing modules with complete lifecycle support. We describe the methodologies and infrastructure necessary to feed pre-silicon design data and intelligence forward into the manufacturing process, and feed manufacturing information back, post-silicon, to inform the design process.

Design technology co-optimization today

The modern semiconductor design-to-fabrication process mainly relies on intra-module validation mechanisms to prevent the propagation of systematic defects. These validation mechanisms include DRC sign-off of the physical design, verification of optical proximity correction (OPC), metrology and inspection gauging the process, and physical failure analysis to confirm electrical diagnosis. Information exchange and co-optimization typically happens during the early process and technology development stage via design-technology co-optimization (DTCO). Later in the process node’s lifecycle, such co-optimization is facilitated by traditional techniques like design-for manufacturability (DFM) and litho-friendly design (LFD).

Because the design-to-manufacturing process takes between six and 18 months, any defects found after manufacturing can require a time-consuming re-spin and complete the full process again. With the more complex design-process interactions we see today at advanced nodes, the incentives to produce defect-free silicon the first time are compelling.

Extended design-technology co-optimization

There has been a strong push by both fabless companies and foundries to have a systematic information exchange and analytics platform overarching various design-to-manufacturing modules with complete lifecycle support. Our answer is the Calibre Fab Solutions products, which use machine learning methods to extend connectedness of design and manufacturing through curated exchanges.