Achieving optimal performance during physical verification

Productivity in physical verification is a multi-faceted objective that requires multiple strategies and technologies. IC design companies must constantly evaluate their process flows, data management, and hardware usage, including working closely with EDA suppliers to ensure accurate, complete, and state-of-the-art tool coverage, and incorporating new technical functionality to extend hardware capabilities and improve runtimes. Our commitment to innovation and continuous improvement enables design companies to continue producing novel, reliable, and high-quality electronic products with confidence to an ever-expanding marketplace.

Optimizing physical verification in IC design requires continuous improvement

As new process nodes are brought into production, and IC design size and complexity continue to grow, EDA suppliers must constantly refine and enhance their tools to ensure IC design companies and foundries can meet schedule, performance, yield, and reliability goals. Multiple strategies, such as rule file and DRC engine optimization, help reduce the physical verification computational workload at all process nodes. New techniques for data format management streamline data transfers and processing, while data hierarchy management further improves computing efficiency. Operational techniques such as parallel and distributed processing ensure optimized use of hardware resources and memory. Techniques and strategies such as these ensure EDA tools operate as efficiently as possible, while retaining the accuracy that is crucial to IC design success.