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Calibre YieldAnalyzer

Bridging the communication gap between design and manufacturing

With the Calibre YieldAnalyzer tool, recommended rule violations and critical areas can be mathematically weighted by yield impact information to prioritize and trade off between issues that have the biggest impact on chip yield.

The Calibre YieldAnalyzer tool extends the SVRF language to support complex mathematical models that relate the metrics of a particular design feature to its yield impact. Results are fed to the Calibre RVE user interface for visualization and reporting within the design environment. This visual display helps the designer see through the fog of DFM rule violations and into the prioritized yield impact so the most important issues can be addressed to maximize yield.

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