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What’s next for SystemVerilog in the upcoming IEEE 1800 standard

The last revision of the SystemVerilog LRM was completed in 2016 and published as IEEE 1800- 2017. In the time since, tool vendors have continued to extend and make clarifying changes to their implementations. That leaves users and other tool vendors with unclear specifications on how to interpret SystemVerilog code. The next revision of the standard (P1800-2023) intends to address many of these issues to keep the language current. This paper reviews high-level goals for this revision and highlights a few key enhancements.