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What’s next for SystemVerilog in the upcoming IEEE 1800 standard

The last revision of the SystemVerilog LRM was completed in 2016 and published as IEEE 1800- 2017. In the time since, tool vendors have continued to extend and make clarifying changes to their implementations. That leaves users and other tool vendors with unclear specifications on how to interpret SystemVerilog code. The next revision of the standard (P1800-2023) intends to address many of these issues to keep the language current. This paper reviews high-level goals for this revision and highlights a few key enhancements.

Questa Verification Solution

The Questa verification solution from Siemens EDA, a part of Siemens Digital Industries Software, continues to evolve in response to the growing complexity of SoC designs. Besides the sheer size of designs, the inclusion of multiple embedded processors and advanced interconnect systems, increasing software content and the configurability required by multi-platform based designs require a functional verification solution that unifies a broad arsenal of verification solutions.

Verification Academy is the most comprehensive resource for verification training.

The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers. The Verification Academy is the most complete UVM Online resource. You’ll find everything you need to get up to speed on UVM, whether it’s downloading the kit(s), the documentation and code examples from the Verification Methodology Cookbook, Academy Forums or online training courses.

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