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Reduce time to tapeout with native IP block visualization in a full-chip context

System-on-chip (SoC) designers must often begin their chip integration process early in the design stage, without waiting for block-level implementations to complete which can create design rule checking (DRC) issues at the SoC level. Simultaneously, as IP owners implement their blocks, contextual issues may exist at the chip level that are not visible to block owners. Both conditions can make debugging difficult and time-consuming. The Calibre® DESIGNrev™ chip finishing platform provides innovative functionality that allows IP designers to visualize and analyze their IP within the context of the full-chip layout throughout the physical implementation process.

Significantly reduce the time and effort needed to visualize and analyze IP within a full-chip context of the IC design layout during chip integration

When an SoC and its component blocks are developed simultaneously, the Calibre DESIGNrev chip finishing platform enables IP designers to visualize all instances of their block within the context of the full-chip layout without having to load the entire design multiple times in-memory, simplifying and speeding up the DRC analysis process for block owners. Enabling block owners to quickly see their blocks in context before actual implementation reduces the time required to confirm the IP meets the overall design specifications and requirements, speeding up the overall design flow while ensuring the SoC satisfies its design goals.