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Verification and validation of embedded software for Arm SoCs

Hardware verification environments are great for verifying hardware but are lacking in bringing more visibility to the hardware-software environment. The key to such visibility is linking the software debugger to the RTL simulation environment.
Adding a software-enabled verification environment to an existing hardware verification environment yields many benefits to designers working on Arm-based designs. Tools available today, such as Veloce Codelink, provide the functionality described. Veloce Codelink does not require changes to software or hardware design and allows for logging and replaying simulation. This multi-faceted tool supports multi-core, multi-CPU environments, and the ability to step forward and backward.

Indeed, adding the debugger to the RTL processor model yields many benefits. Adding the software debugger to the hardware verification environment allows for a higher level of abstraction when writing software. This helps to avoid the tendency to oversimplify the software because of a lack of visibility. Even though C or C++ allow for a higher level of abstraction, programs written in these languages are often very simple, because they are very hard to debug. In the extreme case, such programs work almost at the assembly level, performing basic hardware writes and reads just so they can configure ASIC registers.

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