Veloce's unique & innovative approach for seamless simulation acceleration

The ever-increasing demand for functionality, performance, and bandwidth has forced semiconductor companies to integrate as many capabilities as possible in their ASICs and SOCs. This advancement has become a race where competitors work diligently to reduce the time-to-market yet provide greater functionality and performance.

Even though verifying small designs might just take a couple of hours of simulation, verifying an end-to-end system takes weeks and months of simulation run time. If one delays running the full system tests to later verification cycles, there can be huge costs associated with it, as bugs identified during early simulation verification cycles are easier, quicker, and much cheaper to address than when the chip is close to tape out.

In this paper, we demonstrate the value of the Veloce ecosystem offerings that can help maximize verification environment reuse, identify design bugs quickly, and thus reduce the verification efforts. A comparison using real design highlights the speed gains attained using Veloce offerings. The simulator used for these experiments is Synopsys’ VCS.