A typical UVM testbench
A typical UVM test bench has a device-under-test (DUT), and an “agent” for each interface, an “environment” collecting agents together, and a top level “test”. The interfaces to the DUT are SystemVerilog interfaces – and the virtual interface is used to connect the DUT to the class-based testbench. Don’t worry – the templates will take care of most of this detail and vocabulary.
Two sets of templates have been developed, each with a slightly different focus. The paper will discuss one of the templates only. The other template is available from the authors. There is no right template. Each template will reflect the priorities of the template writers (edit-inplace vs. edit-side-files), or the focus of the verification effort (cover-all-address-ranges vs. cover-addressranges-edges) or the general verification philosophy (read-and-write-all-memory).
The template system itself is a stand-alone runnable – meaning that the template can be compiled and simulated and will do something. There is no DUT connected, and no useful verification will happen, but by being a compile-able and simulate-able system, it is easy to create a template that has fewer bugs to begin with. There is no pseudo SystemVerilog code involved. It is all SystemVerilog UVM.
The templates for this paper consist of about 20 files that have a total of 500 lines. The idea is that the template should be trivially simple. The generator script is to the right.