The smart path to chiplets using hierarchical device planning and pin regions
Advancements in IC packaging manufacturing, combined with the exploding costs of designing monolithic ICs on today’s advanced process nodes, have given rise to a growing trend of disaggregating large SoCs into smaller dies and chiplets. This increased design complexity requires iterative multi-physics analysis during the floorplanning stage and optimization of the design for PPA and cost goals, significantly raising the barrier for project success. Trying to employ traditional package design solutions – where each device is modeled as a single flat entity – is time consuming and unnecessarily risks delaying production.
A collaboration between Intel Foundry Services and Siemens EDA
Heterogenous integration must be addressed at the inception of the IC product life cycle and, thus, mandates a new approach to early design planning for semiconductor package design. Early in technology development, optimizing the pin layout for power, performance, and area take priority. High pin count ASICs/FPGAs get broken down into smaller blocks (IOs, Complex IPs, Cores, AMS blocks etc.) that are instanced many times and are integrated to form the complete floorplan of the ASIC/FPGA or chiplet. This is not only the case for the ICs, but also for interposers and package substrates.
Intel Foundry Services defined this methodology plus use model and partnered with Siemens EDA in the development of a unique set of functions and capabilities integrated into the Siemens package prototyping and planning design tool. In this white paper, we discuss the capabilities and benefits of using this hierarchical device planning approach realized through a collaboration between Intel Foundry Services and Siemens EDA.