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White Paper

The smart path to chiplets using hierarchical device planning and pin regions

Reading time: 5 minutes
Advancements in IC packaging manufacturing, combined with the exploding costs of designing monolithic ICs on today’s advanced process nodes, have given rise to a growing trend of disaggregating large SoCs into smaller dies and chiplets. This increased design complexity requires iterative multi-physics analysis during the floorplanning stage and optimization of the design for PPA and cost goals, significantly raising the barrier for project success. Trying to employ traditional package design solutions – where each device is modeled as a single flat entity – is time consuming and unnecessarily risks delaying production. In this paper, we present a “smart path” to homogeneous disaggregation using hierarchical device modeling and parameterized pin regions.


  • Introduction

  • Floor-planning environment

  • Die-to-die building blocks

  • Arrayed building blocks

  • Power distribution networks

  • Parameterized pin regions

  • Homogeneous disaggregation of SoC

  • Conclusion

  • References

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