Tessent Hierarchical ATPG Reference Flow for Arm Cortex-A75
The Tessent group of Siemens EDA and Arm jointly developed a reference flow for a hierarchical DFT and ATPG implementation with Tessent for any Arm subsystem based on Cortex A-series IP. The reference flow, described in this paper, provides documentation, seamless interfaces, and scripts that accelerate the implementation of a hierarchical test solution. We are both dedicated to enabling customer success, regardless of their level of experience implementing hierarchical ATPG on Arm cores.
