Techniques to identify reset metastability due to soft resets
Detect RDC issues in highly complex reset architectures
A static RDC methodology to prevent silicon respins
Highly complex reset architectures in automotive designs demand a proper verification method to detect RDC issues. These RDC bugs, if ignored, can have severe consequences on system functionality, timing, and reliability. It is essential to detect unsafe RDCs systematically and apply appropriate synchronization techniques to tackle the issues that may arise due to delays in reset paths due to soft resets. Such action ensures proper operation and avoids the associated risks. By handling RDCs effectively, designers can mitigate potential issues and enhance the overall robustness and performance of a design.
This paper presents a systematic flow to assist in RDC verification closure using standard RDC verification tools. The Questa® RDC verification tool using this new methodology identified around 131 reset domains in the design, which consisted of 19 asynchronous domains defined by the user as well as 81 asynchronous reset domains inferred by the tool. The results of this test case are shared in the paper.