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Taking chips to another dimension: 3D-integrated silicon photonic transceiver verification

3D LVS verifies that the signal interfaces between the different levels of substrate hierarchy connect as expected and that any manufacturing or assembly mismatches or signal to pin assignment mistakes are captured.
Texas A&M University and UC-Davis design teams discuss the verification challenges they overcame when co-designing a CMOS transceiver chip directly mounted to an active photonics IC for a United States Department of Energy-funded project.

Why 3D Integration

Silicon photonics (SiPh) has the potential to revolutionize data communication by enabling the integration of photonics and electrical chips while remaining compatible with mature, silicon-based CMOS process technologies. Given the wide-bandwidth and high-speed possibilities of optical data transmission, it can enable highly scalable communication architectures and a seamless transition from die level to system level optical fiber infrastructures. Silicon photonic ICs.

There are unique challenges to overcome with this integration, and new mechanisms are needed for the transceivers that transition data between the electrical and optical domains. SiPh utilizes silicon or silicon nitride-based photonic waveguides for transmission of data signals. This requires dedicated transmitter circuits to control and convert electrical data into the optical signals that are launched into waveguides. Receiver circuits that detect and process optical data signals are also necessary.

The joint project between UC-Davis and Texas A&M University addresses the critical need to reduce the amount of energy dissipated in data movement between compute nodes. The primary goal is to develop an energy-efficient optical transceiver based on a wavelength-division multiplexing (WDM) scheme with multiple 33 Gb/s channels operating on individual optical wavelengths.

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