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SystemVerilog constraints: Appreciating what you forgot in school to get better results

Learn how SystemVerilog constraints work.

This paper looks at two of the most common issues when constraint solver results do not match your intent: Not understanding how Verilog expression evaluation rules apply to interpret the rules of basic algebra and not understanding the affect probability has on choosing solution values. Coding recommendations for improving your code to get better results are provided.

Constrained random verification (CRV) addresses the time-consuming task of writing individual di-rected tests for complex systems. We sometimes say that CRV automates writing tests for quickly producing the test cases you can think of, or hitting the corner cases you didn’t. But the reality is, like with any computer programming language, your code executes exactly the way it is written, and has no concern for what you were thinking. In particular when coding constraints, this manifests as results that satisfy the constraints, but may not match what you intend. Crashes or conflicting constraint failures are usually easier to resolve because of their abrupt termination.

However, without an abrupt termination, you may not notice anything wrong with the results until much later in the process; perhaps after you check your functional coverage reports.

This paper presents a background defining how SystemVerilog constraints work, and how these issues play into getting unwanted results. Also, it offers a few coding recommendations for improving your code to get better results along the way.

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