Challenges with DFT for complex SoCs
The traditional approach to moving scan test data from chip-level pins to core-level scan channels is under pressure due to the dramatic rise in design size, design complexity, and test adaptation. In the traditional approach to delivering scan test data to cores, each core requires a dedicated connection to chip-level pins, which doesn’t allow for much flexibility, as the dependencies between the cores and the chip-level pins are set once during design. In a bottom-up flow, DFT engineers typically allocate a fixed number of scan channels for each core, usually the same number for each core. This is the easiest approach, but it can end up wasting bandwidth because the different cores that are grouped together for testing might have different scan chain lengths and pattern counts. Other problems with this approach include limited IOs available for scan test, limited core-level channels, and potential for routing congestion. A pin-muxed scan approach also does not allow for adjusting to changes in test data over time. For instance, as yield ramps up, some pattern types may no longer be needed for some cores. Or, a different allocation may be needed for wafer test, package test, and in-system test.
The promise of packetized scan test delivery
A packetized scan test delivery like Tessent Streaming Scan Network offers a more effective and tunable approach. The idea is to deliver scan test data across a uniform network that is connected to all cores or blocks in a design. The data that is shifted in and out of the chip does not look like conventional scan test data, but is organized in packets that the network understands how to translate into more conventional-looking scan data at each core. The SSN approach is based on the principle of decoupling core-level test requirements from chip-level test resources by using a high-speed synchronous bus to deliver packetized scan test data to the cores.