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white paper

STMicroelectronics: IP validation and analysis with Solido Crosscheck and Solido Analytics

Solido methodology helps STMicroelectronics ensure IP release quality and improve QA efficiency

Modern system-on-chip (SoC) designs benefit from the integration of design IP as a method of modularizing design workflows, leveraging re-usability of components, and improving design quality as well as time-to-market. IP production teams provide standard cells, I/Os, and many other types of digital and analog IP, including interface blocks, power management units, data conversion IP, etc., to be integrated at the chip-level or higher block levels.

For all of these IP types, effective validation that anticipates SoC integration challenges is important to ensure the final design meets power, performance and area metrics while staying within production schedules and budgets. A strong IP QA methodology achieves this by detecting issues early and improving the quality of the IP used.

This white paper describes how STMicroelectronics utilizes Solido™ tools to deliver a comprehensive solution for IP QA and .lib validation.

STMicroelectronics' requirements for an effective, comprehensive IP QA methodology

To be an effective solution, an IP QA framework must deliver on multiple metrics, including: breadth and depth of validation coverage to meet validation requirements, usability of the solution and effectiveness of analysis/debugging, and finally, extensibility and the ability to integrate into larger production and validation systems, if needed.

In addition, to sign off an IP release as production-ready, STMicroelectronics’ IP team requires an IP QA flow that can detect consistency issues between views (i.e., inconsistencies between LEF versus .lib views), as well as perform view modeling checks, IP integrity checks, and package checks.

Furthermore, for .libs, due to the complexity in .lib data structures and volume of data, the IP QA methodology needs to be able to automatically check for outliers and potential systemic issues, such as issues that affect an entire PVT .lib.