As physical verification checks grow in quantity and complexity, error debugging has become more challenging and time-consuming. Finding innovative ways to present error data more efficiently to designers and SMEs can not only speed up the debugging and error waiver processes, but also minimize the use of valuable engineer time. Consistent, standardized displays would make it easier for SMEs to find and analyze potential error waivers, while also simplifying and speeding up the error debugging process. Designers and physical verification engineers could run more iterations, and review and fix a greater number of violations while staying on schedule. Design teams could reduce time to tapeout while also reducing the risk of suboptimal performance or, worse yet, a post tape-out failure of their chip.
The speed and efficiency with which root cause can be identified is often very dependent on how results data is viewed. CAD rule deck writers typically have a specific intent for organizing and presenting rule check results. However, engineers performing error debugging are often unaware of this intent, and must manually configure the results display, creating an inefficient and ineffective debug that actually extends the time and resources required for debugging.
Creating default view definitions in the results display could make the debug process faster and easier, reducing turnaround time for every iteration. Consistent, standardized displays would make it easier for subject matter experts to find and analyze potential error waivers. Designers and physical verification engineers could run more iterations, and review and fix a greater number of violations while staying on schedule. Design teams could reduce time to tapeout while also reducing the risk of suboptimal performance or, worse yet, a post tape-out failure of their chip.