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Simplifying DFM line-end enhancement with pattern matching

Screenshot showing multiple automated line-end extensions created in an IC design layout.
Failure to address potential manufacturing issues before tapeout can decrease IC yield and increase the likelihood of reliability issues. Adding line-end extensions to an IC design layout is one way to improve yield and reliability, but manually adding these DFM enhancements to a physical verification rule deck requires considerable expertise and time. Using Calibre Pattern Matching technology inside the Calibre DESIGNrev chip finishing platform simplifies and automates this task.

Enhancing IC design layouts with automated line-end extensions based on pattern matching can improve IC design yield and reliability at all process nodes

DFM analysis and placement of IC design layout modifications like line-end extensions are used to improve the manufacturability and reliability of IC design layouts prior to tapeout. However, manually coding these modifications into a physical verification rule deck to ensure DRC-clean results requires deep expertise and significant time. IC designers can use the automated capabilities of Calibre Pattern Matching functionality within the Calibre DESIGNrev chip finishing platform to simplify many DFM enhancement tasks, such as line-end extensions. By graphically capturing layout patterns that illustrate the regions where line extensions should be placed, and adding them to a pattern library, design teams can quickly and easily create a reusable template for line-end extensions. The Calibre Pattern Matching functionality can then output a marker as the line-end extension for each matched pattern found in designs. These templates can also be easily updated as additional contexts are identified, or new process technology nodes are added.

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