Skip to Main Content
white paper

Resolving cell name conflicts for efficient layout hierarchy

Duplicate cell names across multiple IP in an SoC can result in unexpected layout results at the full-chip level, larger file sizes, and the inability to run layout verification tools efficiently in hierarchical mode. The Calibre DESIGNrev tool provides a simple, efficient, automated solution for identifying, renaming, and reporting these cell name conflicts. The outcome is a clear and consistent design process, straightforward chip assembly, a clean and meaningful design hierarchy, faster EDA tool runtimes, and faster time to tapeout.