Questa CDC-FX: Metastability effects delay modeling

With asynchronous clocks common place in today’s ICs, designers need a solution to verify that the design’s functionality is not impacted by the non-deterministic effects of metastability. This paper describes why metastability occurs in designs with asynchronous clocks and analyzes the various methods that designers use to verify that their design is resilient with respect to the effects of metastability. It discusses the efficacy of each of these methods and describes in detail the behavioral model of metastability that is used in the Siemens EDA Questa™ clock-domain-crossing verification solution. It will further present a complete verification methodology describing how designers can use this accurate model of metastability in their RTL simulations and verify that the design correctly handles the unavoidable effects of metastability in silicon.