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Qualcomm achieves faster signoff DRC convergence in P&R with Calibre RealTime Digital DRC

Qualcomm achieves faster signoff DRC convergence in P&R with Calibre RealTime Digital DRC | screenshot of complex IC interface error debug
Qualcomm continually strives to optimize their integrated circuit (IC) design flows to achieve maximum efficiency with the most effective use of resources. Achieving signoff DRC convergence in digital implementation flows at advanced nodes is extremely challenging, due to the number and complexity of design rules, and the increasing functionality in these designs. Qualcomm saw an opportunity to optimize their digital implementation DRC process and achieve faster signoff DRC convergence by adding Calibre RealTime Digital in-design signoff DRC to their design and verification flow.

Achieve faster signoff convergence inside the P&R environment with Calibre RealTime Digital signoff physical verification

Because they can now iterate through Calibre signoff DRC in the implementation environment, Qualcomm designers are eliminating a minimum of three to five DRC closure iterations during every critical design milestone, which can save weeks off the tapeout cycle for large SOC designs. And, because the Calibre RealTime Digital interface uses the same Calibre nmDRC signoff deck and engine used in traditional physical verification flows, Qualcomm can be confident that their designs will meet all manufacturing requirements. No matter which use model they apply, the Calibre RealTime Digital interface enables Qualcomm engineers to spend less time fixing DRC errors, providing more time to create innovative, high-quality designs that reach the market on schedule.

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