Skip to Main Content
white paper

Power Integrity Effects of High Density Interconnect (HDI)

Power Integrity Effects of High Density Interconnect (HDI)
High Density Interconnect (HDI) is being used more often to meet the growing need for more complex designs in smaller form factors. Beyond some of the more obvious electrical effects of using smaller vias, there is also an impact to the power integrity of a board using HDI. This includes different effects of mounted inductances of decoupling capacitors, changes in plane performance due to reduction in perforation from chip pinouts, and the inherent plane-capacitance changes from using dielectrics of various thicknesses. This paper will examine and quantify these effects, using numerous design examples, including a large conventional through-hole design board that was reduced using HDI.

What are High Density Interconnect fabrication basics?

There are three basic elements to HDI fabrication:

  1. Dielectric format: There are nine different general dielectric materials used in HDI processes such as photosensitive liquid dielectrics, polyimide flexible film, thermally cured dry films, conventional FR-4 cores and prepregs, and more.

  2. Via formation: There are 10 types of via formations. Although laser via methods can cope with all four of the typical dielectric structures, photovia and plasma via methods are applicable to only 1 or 2 structures. This is one reason why leaser vias are more widely used today.

  3. Metallization methods: There are 5 different methods of metallizing the IVHs used in HDI processes. They are:

    • Conventional electroless and electroplating Copper

    • Conventional conductive graphite or other Polymers

    • Fully and semi-additive electroless Copper

    • Conductive pastes or inks

    • Fabricating solid metal vias

How does High Density Interconnect aid in power integrity (PI)?

  • A significant reduction in the numbers of vias going through the inner layers of the board increases board real-estate available for routing.

  • The reduction in perforation of the power planes by the large number of anti-pads normally present in a chip pin-out results in a greater area of copper used to feed both AC and DC current to the chip power pins.

  • Less resistance in the current path, both to the chip and throughout the plane in general, results in less areas of high current density on the board.

  • Less inductance leading to the chip pins allows for appropriate switching current to reach the power pins, while also increases the effectiveness of the decoupling capacitors surrounding the IC.

Share