Catapult High-Level Synthesis resource library
Be it deep learning, computer vision, communications, video, or countless other spaces, Catapult is more than just “C to RTL”. ASIC, FPGA or eFPGA, with novel code/functional coverage, class-leading power opt, and formal verification, learn how it enables you to do more, and do it better.
New resources
Success stories
BLUEDOT: Accelerating NN-based DeepField-PQO design using Catapult HLS
Service providers face high encoding costs due to HQ videos demand. BLUEDOT offers AI-based DeepField-PQO filter improving coding efficiency. It uses HLS for fast filter implementation into IP targeted for FPGA, Catapult for ASIC.
LG Electronics: Video Encoder IP Design Optimization and Verification Using the Catapult Platform
Through a new design approach, LGE's SoC Center concluded that adopting Catapult in IP development significantly increases efficiency in terms of time and cost, and plan to increase Catapult use in future IP development projects.
Bosch Visiontec rapidly brings new automotive IP to market using the Catapult HLS Platform
The BOSCH® Visiontec team innovates assisted and autonomous driving technology. This team develops
Chips&Media: Design and Verification of Deep Learning Object Detection IP
Chips&Media decided to adopt a new High-Level Synthesis flow to implement their deep learning algorithm. Enabling them now focus on algorithm and architecture design and reduce painful debugging and expensive computing resources.
Google develops WebM video decompression hardware IP using High-Level Synthesis
This paper will describe the actual use of Catapult High-Level Synthesis (HLS) by the WebM team in the successful implementation of the G2 VP9 and share results and impressions.
Konica Minolta Proves C++ Level Signoff Possibilities Using Catapult HLS Platform
A team at Konica Minolta® has been using the Catapult® HLS Platform for many years to dramatically improve their productivity by coding at the C++ level and using the platform to generate RTL.
STMicroelectronics quickly brings automotive image signal processing to market with High-Level Synthesis
STMicroelectronics crafted a unique High-Level Synthesis flow, enabled by templates, to design and verify an image signal processing (ISP) device, fostering getting it to market as fast as possible.
Qualcomm: Designing ASIC IP at a higher level of abstraction
Paper discussing some of the reasons why this HLS/HLV flow gives companies like Qualcomm several advantages, summarizes the flow and its benefits, and describes how it can provide even more advantageous features in the future.
Working smarter, not harder: NVIDIA closes design complexity gap with HLS
Discover the challenges NVIDIA faces in the ever evolving world of video, camera, and display standards and the reasons an HLS/C-level flow make it possible for them to succeed in this context.
StreamTV’s SeeCubic: Catapult HLS enables Ultra-D 3D without glasses
StreamTV's SeeCubic faced an impossible task: develop a real-time conversion IP block for a custom SoC without knowing the target technology. This IP was critical for their glasses-free 3D solution.
White papers
High-Level Synthesis Enables the Next Generation of Edge AI Accelerators
Delivering AI in today’s IoT systems efficiently goes beyond simply porting neural networks in Python to an edge device. Customized hardware built with High-Level Synthesis will differentiate your system from the competition.
Quantization of HLS Designs Using Value Range Analysis
The process of converting the floating-point algorithm to bit-level optimized model is complicated and requires special knowledge. This paper introduces a simple and robust quantization methodology based on value range analysis.
High-Level Synthesis, it’s still hardware design
This paper talks about who the key individuals are that need to be involved in a successful High-Level Synthesis (HLS) hardware design flow and the challenges of designing using HLS.
Accelerate Computer Vision Design Using High-Level Synthesis
This whitepaper covers the role of convolutional neural networks in computer vision designs, typical coding practices, and how HLS addresses design challenges.
AI Accelerator Ecosystem: An Overview
Catapult HLS offers an AI accelerator ecosystem providing AI designers an environment to jumpstart their projects. This ecosystem provides resources from IP libraries to full toolkits with real working designs.
Catapult for a Power Optimized ESL Hardware Realization Flow
This paper describes, in general, the Catapult® flow for exploring low-power architectures, and it discusses in detail the low-power optimization results achieved using the Catapult Low-Power design flow.
Deploying High-Level Synthesis (HLS) in a DO-254/ED-80 workflow
This paper describes the requirements and considerations to successfully use HLS within a DO-254/ED-80 workflow and how HLS is qualified for safety-critical applications/designs.
Computer Vision Sees a Bright Future
Computer vision is powering advances in automotive, medical, consumer, and agriculture markets. Learn about the computer vision market, why it is growing, challenges and how HLS addresses these challenges.
Closing coverage in a High-Level Synthesis flow
Catapult Coverage brings the coverage solution that RTL teams employ into the HLS world. Check out this whitepaper to learn how to use Catapult Coverage to measure and close coverage in a HLS flow.
Closing Functional and Structural Coverage on RTL Generated by High-Level Synthesis
This paper describes innovative techniques to use with existing methodologies, for example the Universal Verification Methodology (UVM), to close functional and structural coverage on HLS generated code.
Finding Code Problems Before High-Level Synthesis
In order to significantly speed up verification and to handle complex algorithms that change daily, many companies are turning to a High-Level Synthesis (HLS) methodology.
Machine Learning at the Edge: Using HLS to Optimize Power and Performance
Moving machine learning to the edge has critical requirements on power and performance. Using off-the-shelf solutions is not practical.
High-Level Synthesis for autonomous drive
Speed up your design flow and tame the verification challenge using the High-Level Synthesis (HLS) methodology, which in select cases is vastly superior to hand-coded RTL, when creating custom chips for Automated vehicles.
Smoke Testing a High-Level Synthesis Design
Designing hardware using C++ and C++ testbenches brings orders of magnitude speed-up to simulation. But after
Move to a High-Level Synthesis (HLS) Flow to Remain Competitive
In the world of IC design, the RTL flow prevails. But today’s market for state-of-the-art image processing, high-bandwidth communication, and computer vision and neural computing solutions demand another level of abstraction.
A Semi-Canonical form for Sequential AIGs
Collaboration with UC Berkeley to develop an innovative way to detect isomorphisms within logic designs. This work describes a way to use simulation to quickly identify isomorphisms.
Design and verification using High-Level Synthesis (HLS) software
Overview of design, optimization and verification using HLS. Paper outlines some requirements for HLS designs to fit into existing design and verification flows and ways in which these might be adapted with wide HLS deployment.
High-Level Synthesis (HLS): status, trends and future directions
Paper providing perspectives on the ways in which High-Level Synthesis (HLS) is helping and shaping verification, power optimization, and design reuse.
Eigenvalue decomposition using the Catapult Algorithmic Synthesis Methodology
This report discusses the hardware implementation of “eigenvalue decomposition”.
Integrated Circuit Design for New Mobility
Read this paper to learn about integrated circuit (IC) design for new mobility technologies and how advanced design automation and lifecycle management solutions will be crucial to success.
Podcasts
Designing the next generation of AI chips
Designing microchips is a daunting task which is growing increasingly challenging as new algorithms and software push the demand for…
Designing the next generation of AI chips Part 2
As AI grows increasingly integrated with modern products, finding a way to quickly and efficiently design purpose-built AI accelerators for…
Training
Demos and seminars
Documentation and reference designs
Modeling and synthesizing large ratio rate adapters
Complex interpolation/decimation ratios can require very large filters. Here we present an efficient implementation of a 37/50 rate adapter using HLS.
High-Level Synthesis (HLS) Blue Book
A comprehensive guide for designing hardware using C++. It presents the most effective C++ synthesis coding style for achieving high quality RTL. Master a totally new design methodology for coding increasingly complex designs.
Webinars
LG Electronics: Video Encoder IP Design Optimization and Verification Using Catapult
In this session, LGE describes a new design approach which concluded that adopting Catapult in IP development increases efficiency in time and cost, and they plan to increase usage in future IP projects.
NVIDIA: High-Level Synthesis in Agile System-on-Chip Flows: Overview and Techniques
This talk provides a brief overview of NVIDIA Research’s use of Catapult HLS and highlights some useful features and flows of the Connections library, such as the ability to back-annotate SystemC simulations.
Catapult AI NN – From AI/ML Framework to Optimized RTL
Video describing how Catapult AI NN now delivers a methodology and flow from “AI/ML Framework to RTL” enabling rapid exploration of network, quantization, design reuse factors, and more!
High-Level Synthesis Verification Technologies and Techniques
This session will describe applying known and trusted static, formal and dynamic approaches to verification performed at the C++ or SystemC HLS level of abstraction.
Hardware Accelerators – Exploring Power and Performance in Today’s AI
This session explores the design process from algorithm to hardware accelerator on a RISC-V processor as we quantify power consumption and performance.
Nokia: Experience in Adopting HLS and HLV Methodology
For increasing requirements for shorter time to market, Nokia has explored is raising abstraction level in both RTL design and verification with the help of High-Level Synthesis and Verification tools.
STMicroelectronics: In sensor Bricks Multi-objective Optimization of an Algorithm Chain for In-Sensor Processing
Through HLS and their innovative modular system, STMicroelectronics leads in the seamless integration of digital intelligence into analog native products, setting new standards for efficiency and market.
INOVA Semiconductors and Coseda: Paradigm Shift in Mixed Signal ASIC Design, Adopting SystemC and High-Level-Synthesis vs. Traditional RTL Design Flow
The authors will present the ease of use and the value-add of the HLS methodology in an automotive context.
HW Acceleration with High-Level Synthesis
Session introduces High-Level Synthesis, a technology that allows a developer to take a C++ function and automatically compile it into an RTL hardware description, suitable to be deployed into an ASIC or FPGA.
Fermilab: Bridging Machine Learning and Hardware Design with hls4ml and Catapult HLS
Fermilab introduces their partnership with Siemens to provide full integration with Catapult HLS design & verification flow, describe projects that have benefitted from hls4ml, and outline future directions.
Oak Ridge National Lab (ORNL): A Spiking Neural Network Architecture for Ultra-low Power and Ultra-low Latency Computing
ORNL with the help of the Siemens EDA tools, including Catapult HLS, the neuromorphic accelerator is being adapted from an FPGA prototype to a more capable and lower-power ASIC implementation.
How NVIDIA Uses High-Level Synthesis Tools for AI Hardware Accelerator Research
With constant change in AI/ML workloads, NVIDIA leverages a High-Level Synthesis design methodology based off SystemC and libraries like MatchLib to maximizing code reuse & minimizing design verification effort
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Telechips: RTL Hardware Design Acceleration for On-The-Fly Image (De-)Warper in Automotive SoC Using C++ HLS
Telechips designed a new dewarping engine processing video stream data on-the-fly, different from traditional GPU-based memory-to-memory approach, by utilizing hierarchical design methodology in Catapult HLS.
STMicroelectronics: A Common C++ and UVM Verification Flow of High-Level IP
STMicro presents a unified way to integrate the definition of RTL and C functional coverage and assertion (reducing the coding effort) and a method to add constraints to the random values generated in UVMF.
Infineon: HLS Formal Verification Flow Using Siemens Formal Verification
High-Level Synthesis (HLS) is design flow in which design intent is described at a higher level of abstraction such as SystemC/C++/Matlab/etc.
CEA: Bridging the Gap Between Neural Network Exploration and Hardware Implementation
CEA presents a methodology that bridges the open-source DL framework N2D2 and Catapult HLS to help reducing the design process of hardware accelerators, making it possible to keep pace with new AI algorithms.
High-Level Synthesis & Advanced RTL Power Optimization – Are you still missing out?
Discover how C++ & SystemC/MatchLib HLS is more than just converting SystemC to RTL. In the RTL Design space, we will cover our technology for Power Optimization with PowerPro Designer & Optimizer.
Infineon & Coseda: Facelifting a SystemC System Level Model Towards Physical Prototype – Adoption of High-Level-Synthesis
Infineon & Coseda present on the adoption of High-Level-Synthesis at an existing SystemC system level model.
Ultra Video Group (Tampere University): Managing the Complexity of an HEVC Encoder (Kvazaar) Implementation on FPGA with Catapult HLS
Dr. Panu Sjövall from Ultra Video Group (Tampere University), sheds light on how they were able to implement their embedded real-time HEVC intra encoder (Kvazaar) on HW with Catapult HLS.
Quantization of HLS Designs Using Value Range Analysis
Introduces simple & robust quantization methodology based on value range analysis. Learn what’s fixed-point conversion a.k.a quantization; dynamic & static quantization methods; and how to use Catapult VRA.
DUTh: Architectural Improvements for Low-Power and Functional Safety of Dataflow CNN Accelerators Using HLS
DUTh demos using HLS to design CNN accelerators with on-line checking capabilities, improve power efficiency due to optimized data handling on spatial variants of convolution, and effectively use HLS.
Alibaba: Innovating Agile Hardware Development with Catapult HLS
At the IP level, an ISP was created within a year using Catapult, a task impossible using traditional RTL. To reduce dependency on designer experience, Alibaba introduced an AI-assisted DSE tool.
Cornell University: Building Sparse Linear Algebra Accelerators with HLS
Cornell intros HiSparse: accelerator on sparse-matrix dense-vector multiplication. Using both HLS implementation and simulation, their sparse accelerators deliver promising speedup.
FNAL: Ultrafast Neural Networks for On-Detector Edge Processing in Resource-Constrained Extreme Radiation Environment
FNAL demos that a NN autoencoder model can be implemented in a radiation-tolerant ASIC to perform lossy data compression. This alleviates the data transmission problem.
Harvard University: Effective SW/HW Co-Design of Specialized ML Accelerators Using Catapult HLS
Harvard sheds light on their agile algo-hw co-design & co-verification methodology powered by HLS. It led to an order of magnitude improvement in the design effort across 3 generations edge AI accelerator SoCs.
Stanford University: Edge ML Accelerator SoC Design Using Catapult HLS
Describes the design and verification of the systolic array-based DNN accelerator taped out by Stanford, the performance optimizations of the accelerator, and the integration of the accelerator into an SoC.
From Simulink to High-Quality RTL using High-Level Synthesis - The Design Methodology
Webinar introducing a design methodology starting from a flat floating-point Simulink model and step through to HLS generated RTL. All design steps including fixed-point conversion are described in detail.
From MATLAB® to High-Quality RTL Using High-Level Synthesis - The Design Methodology
Webinar introducing a design methodology that starts from a self-contained MATLAB script and goes through the different workflow steps to HLS generated, high-quality RTL. All design steps are detailed.
High-Level Verification of an AI/ML Accelerator Design
This webinar demonstrates how one can achieve comprehensive verification faster at a higher level of abstraction but still apply known and trusted RTL verification techniques.
HLS 101 - What Every RTL HW Design Team Needs to Know
High-Level Synthesis (HLS) extends the traditional design flow, providing a new and powerful approach to hardware design. It is important to understan
Microsoft - HLS Hardware Design Patterns
High-Level Synthesis (HLS) using untimed C++ presents an elegant hardware abstraction framework for simplifying hardware design at the unit level. To
Doing Research with Catapult HLS at Harvard
One of them is about proposing adaptive floating-point (FP) quantization to replace integer (INT) quantization for NNs.
NVIDIA: Design and Verification of a Machine Learning Accelerator SoC Using an Object-Oriented HLS-Based Design Flow
A high-productivity digital VLSI flow for designing complex SoCs is presented in this webinar. It includes High-Level Synthesis tools, an efficient im
Leveraging HLS IP to Accelerate Design and Verification
Webinar about how leveraging HLS IP and reference designs to accelerate AI and Image/Signal Processing.
Porting Vivado HLS Designs to Catapult HLS Platform
This webinar will cover how to port an existing HLS design developed within the Xilinx® Vivado® HLS environment into Siemens' Catapult® HLS Platform.
Early AXI4 SOC Performance Verification Using NVIDIA MatchLib and Catapult HLS
This webinar will introduce NVIDIA Matchlib and its usage with Catapult HLS using some AXI4 SOC demonstration examples.
From HLS Component to a Working Design
Complex algorithms do not exist in a vacuum. After High-Level Synthesis (HLS) is used to create an RTL component, to be useful, it needs to be integra
Part 1: Why Are High-Performance Low-Energy Applications Moving from GPUs and DSPs to FPGAs and ASICs?
Transistor counts and performance of integrated circuits are reaching their peak. Artificial intelligence is emerging as the next "big thing" in areas
Part 2: Adapting software algorithms to hardware architectures for high performance and low-power
GPUs and DSPs offer very high-parallelism and impressive memory bandwidths, within the scope of a fully programmable platform. However, they need to f
High-Level Verification: Verification Methodology and Flows When Using C++ and HLS
Highlights proven tools and methodology that help an HLS designer check and verify his design, measure, and close coverage, and compare the C to RTL implementation.
Building an iDCT for H.265 Using High-Level Synthesis
High-Level Synthesis (HLS), has been adopted by leading companies to speed design time and reduce verification costs in applications such as video and
Catapult HLS for RTL Teams - What You Need to Know
Catapult® HLS is a key competitive technology in several emerging markets like machine learning and vision. In this webinar, we cover both an introduc
Implementing Machine Learning Hardware Using High-Level Synthesis
Neural networks are typically developed and trained in a high-performance 32-bit floating-point compute environment. But, in many cases a custom hardw
Using high-level synthesis to accelerate computer/machine Vision applications
High-Level Synthesis (HLS) has been used in multiple companies, projects, and designs targeting vision processing for the past several years. HLS adop
Using HLS to Accelerate Computer Vision for Autonomous Drive
The algorithms to teach a computer to see, understand and make decisions for ADAS and Autonomous Drive systems require a significant amount of paralle
Stanford/AMD: Automated Methodology for Efficient Hardware Accelerator
Mobile devices today are composed of many specialized accelerators to achieve high-performance and low-power specifications. However, accelerator desi
Machine Learning: How HLS Can Be Used to Quickly Create FPGA/ASIC HW for a Neural Network Inference Solution
This session reviews the consideration around fast HW prototyping for validating acceleration in Neural Networks for Inferencing vs highest performance implementation and the tradeoffs.
Neural Network Quantization for Low-Power
This webinar will describe how to use Qkeras and High-Level Synthesis to produce a bespoke quantized CNN accelerator, and compares the accuracy, power, performance, and area of different quantizations.
Moving Between FPGA and ASIC with High-Level Synthesis
Writing RTL that works smoothly on both FPGA and ASIC implementations is nearly impossible. But, High-Level Synthesis (HLS) can make technology-indepe
Solutions for the Design and Verification of 5G SoCs
Catapult, Veloce 5G Fronthaul, Veloce X-STEP, Questa