Technical Paper

Parasitic extraction technologies for advanced node and 3D-IC design

Parasitic Extraction Technologies for Advanced Node and 3D IC Design

The Calibre xACT solution offers parasitic extraction options for interconnect modeling that ensure accurate capture of parasitic and layout-dependent effects for non-planar devices in advanced node designs, simultaneous multi-corner extraction for efficient processing, and accurate identification of EM current density violations, as well as accurate extraction and modeling for 3D-IC package designs.

Share

Related resources

STMicroelectronics quickly brings automotive image signal processing to market with High-Level Synthesis
White Paper

STMicroelectronics quickly brings automotive image signal processing to market with High-Level Synthesis

STMicroelectronics crafted a unique High-Level Synthesis flow, enabled by templates, to design and verify an image signal processing (ISP) device, fostering getting it to market as fast as possible.

Working smarter, not harder: NVIDIA closes design complexity gap with HLS
White Paper

Working smarter, not harder: NVIDIA closes design complexity gap with HLS

Discover the challenges NVIDIA faces in the ever evolving world of video, camera, and display standards and the reasons an HLS/C-level flow make it possible for them to succeed in this context.

Google develops WebM video decompression hardware IP using High-Level Synthesis
White Paper

Google develops WebM video decompression hardware IP using High-Level Synthesis

This paper will describe the actual use of Catapult High-Level Synthesis (HLS) by the WebM team in the successful implementation of the G2 VP9 and share results and impressions.