Skip to Main Content
white paper

Packetized scan test

Take a leap forward in DFT for complex SoCs with Tessent Streaming Scan Network

Tessent Streaming Scan Network ushers in a new era of IC test efficiency for today and tomorrow.
Bus-based packetized scan data decouples test delivery and core-level DFT requirements so core-level compression configuration can be defined completely independently of chip IO limitations. Grouping cores for concurrent testing is selected programmatically, not hard-wired. This concept dramatically reduces the DFT planning and implementation effort.

The Siemens solution for packetized delivery of scan test patterns, Tessent™ Streaming Scan Network (SSN), is a significant advancement in DFT for today’s complex SoCs. It enables simultaneous testing of any number of cores with few chip-level pins, plus reduces test time and test data volume. With SSN, DFT engineers have a true SoC DFT solution without compromises between implementation effort and manufacturing test cost. SSN also enables the implementation of a IEEE 1838 Flexible Parallel Port for testing 3D ICs. This paper describes the basic components of the SSN and presents short case studies of its use.

Streaming Scan Network solves scan distribution challenges in complex SoCs

Today's DFT engineers face challenges with the traditional pin-mux scan test approach that include:

  • Planning and layout

  • Effective handling of identical cores

  • Tile-based designs with abutment

Tessent Streaming Scan Network (SSN) solves these challenges by decoupling test delivery and core-level DFT requirements. With SSN, compression and number of scan channels for a core is determined based on what results in the most compact pattern set for that core by itself.

The SSN implementation flow is based on Tessent Shell flow for hierarchical designs. SSN is fully supported by Tessent TestKompress™ and Tessent Diagnosis, and can co-exist with all other Tessent DFT technologies such as Tessent MemoryBIST and Tessent LogicBIST.

Share