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Package designers need assembly-level LVS for HDAP verification

While advanced IC packaging is a fast-growing market, comprehensive package verification still has a ways to go. Unique package connectivity issues, such as missing or misplaced interposer/package bumps/pads, pin naming and text labeling issues, and the like, require new and enhanced LVS-like verification techniques that can move across the entire package to ensure proper connectivity and performance. With its native support for packaging file formats, automated analysis of HDAP connectivity verification requirements, and integrated assembly-level DRC and LVS checking, the Calibre 3DSTACK tool provides a significant advantage over traditional SoC LVS flows.