white paper

Overcoming SerDes Design and Simulation Challenges - Part 2

Overcoming SerDes Design and Simulation Challenges - Part 2

Examining data over the last 15 years, you can see that off-chip communication energy efficiency improved from 2000-2010 due to supply voltages and process scaling that followed Moore’s Law. Then progress slowed down. Why? Designers are trying to push more data at higher data rates through existing communication channels. Therefore, research is underway to improve power dissipation at the circuit design phase.

Share

Related resources