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Out of the verification crisis

Improving RTL quality

IC verification and validation cost by process node feature size.
A verification crisis is upon us that will not be solved solely through improvements in verification methodologies and techniques. The solution requires a holistic and philosophical change in the way we approach design with a foundation based on bug prevention. Our proposed first step in implementing this change tightly integrates static analysis into the design process, resulting in a decrease in bug density, which has a positive impact on downstream processes and consequently reduces cost.

The Crisis

In 1997, SEMATECH set off an alarm in the industry when it warned that IC manufacturing productivity gains were increasing at a 40% CAGR, while IC design productivity gains increased at only a 20% CAGR. This concern was reiterated in the International Technology Roadmap for Semiconductors 1999 report [1]. Despite these alarms concerning the gap between silicon capacity and design capabilities, the industry avoided this crisis. Why? There were two primary contributors that prevented the design productivity gap: (1) continual improvements in design automation and (2) the emergence of a silicon IP economy that fueled a productive design reuse strategy [2].

In the last decade, a more ominous productivity gap has emerged with respect to verification. While silicon complexity grows at the Moore‘s Law rate, verification complexity grows at a significantly greater rate , and the approaches that were used to close the design productivity gap will be insufficient in closing the verification productivity gap. IBS [3] quantified the impact of today’s verification gap in terms of IC project’s verification and validation cost with respect to decreasing process node feature size, as shown in Fig. 1.

Additional industry studies have measured the verification productivity gap’s impact on IC projects, such as the 2020 Wilson Research Group functional verification study [4]. For example, since 2007, the mean peak number of design engineers working on a project has increased by 32%, while the mean peak number of verification engineers has increased by an alarming 143%. In fact, today there are more verification engineers on average working on an ASIC/IC project than design engineers. Yet even with the increase in project headcount, 66% of all ASIC/IC projects experience one or more respins, while 83% of FPGA projects experience one or more non-trivial bug escapes into production [5]. In addition, two thirds of all ASIC/IC and FPGA projects miss their originally planned schedule. Clearly, a verification crisis is upon us.

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