ON Semiconductor Reduces Memory BIST Insertion Time by 6X with Tessent Hierarchical Flow
This paper describes a case study on the insertion of memory BIST for an ON Semiconductor multi-million gate-level netlist with 300 memory instances. The physical implementation will be done using a flat layout. Two different methodologies can be applied when it comes to physical implementation; hierarchical or fullflat. When performing physical implementation as full-flat flow, typically the DFT methodology also follows the same decision. Thus, DFT is to be inserted once for the entire gate-level design.