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Olivetti eliminates months of ASIC design effort

HDL Designer improves teamwork

Reading time: 8 minutes
The ASIC design group at Olivetti I-Jet in Yverdon-les-Bains, Switzerland designs ASICs for their inkjet printer controllers. Projects like these, including prototyping the ASIC functionality on an FPGA before handing the design off to the ASIC vendor, must routinely be completed within a short six-to eight-month cycle. To manage the design process, the team standardized on HDL Designer Series™.

The design task

The design team employs HDL Designer Series to accelerate the implementation, debug, documentation, and management of their multimillion gate ASIC designs. They use the HDL Designer Series in every aspect of their project: from front-end design and controlling design iterations, through managing their IP portfolio and verifying the FPGA prototype, to finally preparing the design databases before shipment to the ASIC vendor.

Each six- to eight-month project involves the design of a million-gate ASIC for use in the company’s inkjet printer controller cards. The team begins with the design specification, developing the custom blocks needed, combined with existing company IP to develop the RTL description of the ASIC. Once the high-level description has been completed, design verification can begin using simulation.

Prototyping the ASIC with FPGAs is crucial to the Olivetti’s design verification process. The design is completed hierarchically, allowing the design to be easily partitioned into multiple FPGAs. Next, using an internally developed prototyping board populated with several FPGAs, processor, and memory blocks, the design code is verified in hardware. Once the hardware verification is completed, the entire design is re-verified using the ASIC vendor’s sign-off simulator.