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white paper

Mixed-signal verification of an EESY-IC high-speed ADC with Symphony

Using Symphony to verify high-speed ADC chips in the subsampling of RF signals for software-defined radio applications

EESY-IC chose the Symphony Mixed-Signal Verification Platform to overcome its verification challenges that included meeting their verification requirements with high accuracy and fast runtimes, while at the same time being easy to set up and use.
Sensor readout ASIC-based on a delta-sigma ADC
This white paper outlines a new mixed-signal verification flow used at EESY-IC. EESY-IC selected the Symphony platform for its mixed-signal verification flow to verify high-speed ADC chips used in the subsampling of RF signals for software-defined radio applications.

The high-speed ADC chips have a high analog content with digital controllability and require simulating large mixed-signal netlists with long simulation times and very high accuracy. Symphony gives the EESY-IC design team the ability to verify full-chip, mixed-signal designs in a few hours with desired accuracy, providing them more than 10 times the productivity over their previous flow.

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