Detecting and resolving the true on-wafer hotspots (defects) is critical to improve wafers’ yield in high-volume manufacturing semiconductor foundries. As the integrated circuits process becomes more and more complex with the technology scaling, optical rule check (ORC) alone can no longer identify the outlier-alike defects, that is, hot yield killer defects. Failing to detect yield-killer defects could be due to the lack of sufficient understanding and modeling in terms of etching, chemical-mechanical polishing (CMP), as well as other inter-layer process variations. In this paper, we present a fast and accurate defect detection flow with machine learning (ML) methodologies to address the compounding effects from different process stages.
Model building with machine learning
There are three parts in the defect detection ML model building flow:
We use a limited amount of known defects found on wafer as input to train the ML model, and then apply the ML model to the full chip for prediction. The wafer verification data showed that our flow achieved more than 80% of defect hit rate with engineered feature extractions and ML model for an advanced technology node mask. The wafer results showed that machine learning has the capabilities of identifying new types of defects patterns and high-risk repetitive patterns such as SRAM.