Is there a more efficient solution for SERDES channel analysis (or design)?
The complex task of designing a serialization – deserialization (SERDES) channel has become even harder in recent years. For example, industry protocols such as PCI Express (PCIe) Generation 4 and Universal Serial Bus (USB) 3.1 have doubled their signalling rates in a single technology generation. The increased data rates have forced the industry to adopt new methods, such as channel operating margins, for interface analysis. Yet, to minimize costs, board materials have remained the same as they were in previous generations of technology.
