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white paper

New innovative way to functionally verify heterogeneous 2D/3D package connectivity

Silicon IC Semiconductor array photo
Historically IC package design has been a relatively simple task which allowed the die bumps to be fanned out to a geometry suitable for connecting to a printed circuit board. The package netlist was often captured by the package designer, typically using Excel to manually assign net names to the desired die bumps and BGA balls to achieve the intended connection.

Modern package and interposer design has become a system integration task: designers have the responsibility to take input from various stake-holders – who are often designing their content at the same time the package or interposer is being designed – and create a design which is both electrically and physically correct and functions as designed.

Verifying package connectivity for package designs

Functional verification of package connectivity requires an innovative way to exhaustively verify all interconnections between IC blocks using formal verification.

Key requirements:

  • Set up for running the formal tools should be simple, only needing a few minutes.

  • The connection extraction and package connection verification must be fast and work on big systems that have many dies.

  • The methodology should require minimum manual work.

  • Once the setup is done for one design, it can be reused for other designs with minimum tweaking, such as changing the design name and source file list.

Discover how utilizing a formal flow for connectivity verification early, right after package planning and prototyping dramatically improves the quality of the physical implementation and significantly shortens the time to market.

Download the white paper now!

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