One-time IC design metadata generation significantly reduces runtime and resources usage
Whether a design is being optimized for enhanced functionality or improved performance, the sign-off qualification process generally requires re-running all of the physical validation flows, as well as circuit validation and reliability verification flows. In each flow, metadata is repeatedly generated, even when that input design data is unchanged. With the growth in VLSI design requirements and process complexity, these validation flows become more complicated and require more time.
The Calibre PERC reliability platform enables designers to generate design metadata one time during the initial verification flow. When checks must be re-run, that metadata is pragmatically reused to skip steps in which the data is untouched. By preserving, inheriting, and reusing design metadata generated in previous runs, the Calibre PERC reliability platform enables faster turnaround time for complex geometrical checks during rechecking runs. Both runtime and resources utilization are significantly reduced, while the accuracy of the results is unchanged. Debugging, DFM optimization, and FA also benefit from this reuse of metadata, contributing to an overall reduction in turnaround time while ensuring and optimizing design quality.