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White Paper

Improving the reliability and performance of RF ICs with advanced EDA technology

RF circuits are very sensitive to parasitic elements and layout-dependent effects, so both pre- and post-layout simulations are essential to creating a robust circuit that performs reliably over a broad range of operating conditions. However, both time and resources can be reduced by completing verification and debugging of device type, device properties, orientation, symmetry, and other critical design parameters before performing intensive runtime simulations. Calibre tools automate a variety of complex processes to help designers perform accurate, fast verification and DFM optimization of RF ICs.

Topological checking of RF circuits ensures the correct type of circuit structures are used where required, and that appropriate connections are made with these structures. Automated checking of subtle layout-dependent errors in a layout implementation, such as device asymmetry and mismatches, missing dummy devices, common centroid inaccuracies, current orientation matching, etc., minimizes the effects of crosstalk, shallow trench isolation, well proximity effects, and more. Automated post-layout fill optimization ensures symmetric and consistent fill patterns.