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Improving design reliability: LEF/DEF IO ring check automation

Designing complex SoCs requires careful consideration when planning IO pad rings. IO ring rule constraints for these rules vary between foundries, technology nodes, and IP companies. While each IP company supplies detailed rules for IO ring layout, what is not generally available are instructions for applying those rules in the presence of other IPs. Foundry design rule manuals contain detailed guidelines and specifications for pad cell placement to protect against ESD. SoC designers must achieve the desired ESD protection across the SoC while incorporating all of the dissimilar cells and their unique rules. The Calibre PERC reliability platform provides an automated IO ring checking framework to confirm the validity of the IO pad ring placement.

A holistic, integrated, automated approach to SoC IO ring placement verification

In collaboration with ARM, Siemens EDA developed an automated framework to verify SoC compliance with IO placement rules, using the CalibreĀ® PERCā„¢ reliability platform. The Calibre PERC platform can combine both the geometrical and electrical constraints of a design to perform complex rule checks that incorporate layout restrictions based on electrical constraints or variations. This flexible and automated approach to IO pad ring placement verification allows designers to focus on their design, using the IO ring checking framework and the Calibre PERC reliability platform to confirm the validity of the layout they create. The ability to perform this validation on LEF/DEF designs allows early completion of this task in the design cycle, while there is still an opportunity to optimize and refine the design before beginning final signoff verification.