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Hierarchical DFT in a RISC-V Processor

This paper demonstrates the application of the Tessent hierarchical DFT and ATPG methodology on a RISC-V processor. With hierarchical DFT, all the DFT is completed at the block level and then replicated to the top level. Using a RISC-V test case, we show how to insert Logic BIST, Memory BIST, scan cells, TAP, and an in-system controller as well as perform ATPG. Hierarchical DFT moves the DFT efforts early in the design flow and reduces ATPG runtime and compute resources by 10X.

RISC-V is being used in IC designs for artificial intelligence (AI), embedded, graphics engines, networking, storage, and security. Design tools, like the Tessent DFT family, are in place to support designs that include RISC-V cores. Because these processors are used as cores in large, complex designs, it’s important to implement strategies that reduce DFT and ATPG time and cost. This paper demonstrates the application of the Tessent hierarchical DFT and ATPG methodology on a RISC-V processor. With hierarchical DFT, and an in-system controller as well as perform ATPG. Hierarchical DFT moves the DFT efforts early in the design flow and reduces ATPG runtime and compute resources by 10X.

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