The WebM project defines an open file format designed for the distribution of compressed media content across the web. Google is a major contributor to the WebM project, having recently undertaken the design and development of the first hardware decoder IP for WebM, otherwise known as the VP9 G2 decoder. This royalty-free hardware IP enables companies developing multimedia system-on-chip (SoC) designs to deliver next-generation performance and power efficiency, enabling up to 4K (2160p 60FPS) resolution playback on consumer devices such as smart TVs, tablet computers and mobile telephones, as well as traditional personal computers and laptops. The VP9 G2 IP has been implemented with a completely new hardware architecture, coded and verified primarily in standard C++ and synthesized to register transfer level (RTL) logic for different target technologies and performance points using Siemens EDA, a part of Siemens Digital Industries Software’s Catapult High-Level Synthesis (HLS).
This paper will describe the actual use of Catapult High-Level Synthesis (HLS) by the WebM team in the successful implementation of the G2 VP9 and share results and impressions. It presents the HLS methodology used to develop the VP9 G2 hardware decoder and explains how it supports the goals and strategies of the WebM project. It explains why the HLS approach makes design implementation and verification 50% faster than a traditional RTL design flow, and how it enables design teams with different end products to collaborate and contribute to the same IP.