Finding systemic issues before SoC integration speeds time to tapeout
Early detection of systemic design issues, such as power to ground and bridge shorts, enables design teams to fix them before SoC integration and full-chip physical verification. The Calibre FDI utilities provide design teams with a fast, automated flow to perform such checking during implementation, with a minimal amount of user setup, prior to full-chip data merging. Adding this type of design integrity checking to the verification flow can significantly reduce the time and resources needed to ensure systemic errors are removed prior to tapeout.
