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Finding a perfect balance between flexibility and quality in SRAM layouts

SRAM verification is a challenging, yet critical part of SoC tape-outs. The challenge for SoC designers at advanced nodes is to balance their need to customize SRAM blocks to obtain better performance, against the potential impact of those changes on yield. Debugging SRAM modification errors efficiently requires designers to be able to quickly and precisely locate an SRAM error and determine the correct fix. By enhancing the SRAM debugging process with pattern matching and similarity checking, We enable SRAM designers to find a better, more precise balance between design flexibility and yield.