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Evaluating SRAM memory redundancy with Calibre critical area analysis

Chart showing that critical area (square microns) increases as a function of defect size (nanometers) for one defect type.
Redundant elements are often added to embedded memories to improve final yields of IC designs. However, if that redundant memory has no benefit, then die area and test time are wasted, which actually increases manufacturing cost. Want to know if your redundant SRAM memory elements are actually useful, or a waste of time and money? Learn how Calibre YieldAnalyzer critical area DFM analysis can help you determine the optimal redundancy level for your SoC design.

Calibre YieldAnalyzer critical area DFM analysis helps IC and SoC designers determine the right amount of redundant memory needed to improve yield while minimizing die area impact and test time

SRAM embedded memory often encompasses 40-60% of IC design area. Densely packed structures in memory cores make them very susceptible to random defects, so redundant memory elements are often added to embedded memories to improve final yields. However, if redundancy is applied where it has no benefit, then valuable die area and test time are wasted, actually increasing manufacturing cost. The Calibre YieldAnalyzer tool provides critical area analysis (CAA) DFM functionality that enables designers to perform a detailed analysis of IC and SoC memory redundancy, enabling them to accurately quantify the yield improvement they can achieve while minimizing impact on chip area and test.

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