Ensuring robust ESD protection in IC designs
Calibre PERC reliability verification provides automated ESD protection checking
With its unique ability to combine physical and electrical information for accurate analysis of potential ESD conditions in designs, the Calibre PERC reliability platform provides efficient, accurate, automated checking of ESD protection requirements, even in complex SoC designs with billions of transistors. The Calibre PERC reliability platform can automatically identify and accurately analyze design topologies in the input schematic or layout design. Effective resistances and current densities along ESD discharge paths can be calculated accurately and quickly, and any errors can be conveniently viewed and debugged in the familiar Calibre results viewing environment, ensuring complete and correct ESD protection for any IC design. Many leading semiconductor foundries now provide Calibre PERC rule decks, eliminating the need for customized rule decks and providing a standardized, repeatable, and efficient reliability verification process capable of verifying the most challenging reliability issues from first schematic, through SoC assembly, to the final layout.