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Enhancing IO ring checks for consistent, customizable verification

Diagram of an IO ring SoC design containing a digital core, analog IP, and 2 different interface IP. The IO ring cells are four different colors to represent different IO ring constraints for the IP.
Reliability verification faces some unique challenges in SoCs. IP used in a SoC often comes from multiple specialized IP suppliers. IO placement rules are based on the IP design architecture and the IP provider’s expertise and experience. SoC designers must create an SoC IO ring that not only provides the necessary reliability protection across the entire SoC, but also integrates all of the disparate IO ring rules for the IP in the SoC. The Calibre PERC reliability platform’s innovative and unique ability to correlate both netlist and layout (GDS) information supports an automated LEF/DEF IO ring checker framework that enables SoC designers to verify SoC compliance with a wide variety of foundry and IP ESD placement rules.

Automating LED/DEF IO ring checking streamlines IC design reliability verification in complex SoC designs

In place of extensive textual guidelines, IP providers can use the Calibre PERC IO ring checker XML-based framework to provide their IO placement rules and define their IP placement constraints in an input constraint file, without any knowledge of Calibre PERC rule coding. These constraint files can be quickly assimilated into the SoC IO ring check ruleset for use with Calibre PERC reliability verification. The Calibre PERC packaged check flow enables designers to quickly and easily select, configure, customize, and combine multiple pre-coded checks. By replacing manual checking with the IO ring check package, designers are assured of complete and accurate coverage of all IO placement requirements, while the ability to easily customize the checks allows them to satisfy any unique requirements of their designs. In addition, the ability to run on the first LEF/DEF floorplan generated with place and route tools provides an early check for full coverage of IO ring placement rules, enabling any needed changes to be made with minimal impact on the layout, and providing designers the opportunity to optimize and refine the design before final signoff verification.

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