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A CDC protocol methodology to avoid bugs in silicon

Don’t forget the protocol!

Don’t forget the protocol! CDC methodology to avoid bugs in silicon
Designers add synchronization logic to prevent the propagation of metastable events, but often designers do not implement or verify the correct CDC protocol. Without a correctly implemented protocol, a CDC structure will not function correctly and lose or corrupt data or propagate metastability. In this paper, we discuss the difficulties encountered with traditional CDC protocol verification methodologies and present an innovative, complete methodology to overcome the current challenges.

What are CDC protocols and why are they needed?

Although CDC synchronization structures are required to prevent metastability on CDC paths, designer may overlook the fact that a good structure alone is not sufficient to avoid CDC errors. If a CDC synchronizer is not used correctly, the CDC path may experience data loss or data corruption or in the worst case, metastability. The rules that define the correct usage of a CDC synchronizer are called CDC protocols.

In the simplest protocol case, a 2DFF synchronizer requires a stability protocol where the TX data must be held stable for at least 2 RX clock cycles in order for the RX register to reliably capture the TX data and prevent data loss or data corruption. In a more complex protocol case, a data-mux (DMUX) synchronizer requires that the TX data must be stable when the mux enable is active and allowing the RX register to sample the TX data. If the DMUX synchronizer protocol is violated, the RX register will become metastable even though a correct DMUX structure was implemented.

CDC protocol errors must be identified and addressed early in the design cycle, otherwise they can lead to functional failures in later stages. These functional failures can further result in increased iterations and even silicon re-spins. To ensure such issues are not missed, designers and verification engineers verify synchronizer protocols by generating assertions or synchronizer protocols and verifying them using formal model checking and simulation techniques.

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