Discontinuities Are Driving Innovation in 3D-IC Package Design and Verification

Disruption and discontinuity are often the hallmarks of progress. Multi-chip packages (MCP) or System-In-Package (SiP) have existed for many years, however traditional 2D design approaches are increasingly stressed to achieve the levels of integration and form factors demanded by the market. 3D integrated packages allows for tight heterogeneous integration that offers similar performance and size to monolithic SoC and are a fast-growing segment of semiconductor industry. This paper explores the disruption and challenges such 3D integrated packages bring to the design tools, design flows and the verification and signoff required to achieve the yields and performance expected.