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White Paper

Data integrity checks save time and resources in parallel IC design flows

Parallel IC design implementation flows rely on a strategically planned methodology that in turn relies on accurate data throughout the flow to deliver high-quality, next-generation system-on-chips to the market on schedule. Failure or delays at any point prevent individuals and teams from hitting critical milestones, which then creates downstream schedule delays. Lapses in data synchronization between abstract and physical design elements frequently impacts design teams collaborating in parallel IC design flows. Automated data integrity checks ensure quick and accurate identification and resolution of data mismatches before physical verification, eliminating costly schedule delays and rework that can impact time to market.

Data integrity checks compare abstract (LEF/DEF) and physical IC design (GDS/OASIS) databases to eliminate data mismatches before physical verification, reducing schedule delays and rework

One persistent cause of IC design and verification schedule delays is when abstract block representations used in the chip-level floorplan (LEF/DEF data) fall out of synchronization with their physical GDS/OASIS counterparts. Any mismatches between block footprints, pin locations, or layer contents often create significant numbers of errors in the physical verification output that are difficult to resolve. The Calibre nmPlatform provides database conversion, mapping, and comparison utilities that automatically identify and report data mismatches. These data integrity checks enable design teams to resolve data differences quickly and easily before beginning physical verification, reducing the risk of schedule delays.