Data integrity checks compare abstract (LEF/DEF) and physical IC design (GDS/OASIS) databases to eliminate data mismatches before physical verification, reducing schedule delays and rework
One persistent cause of IC design and verification schedule delays is when abstract block representations used in the chip-level floorplan (LEF/DEF data) fall out of synchronization with their physical GDS/OASIS counterparts. Any mismatches between block footprints, pin locations, or layer contents often create significant numbers of errors in the physical verification output that are difficult to resolve. The Calibre nmPlatform provides database conversion, mapping, and comparison utilities that automatically identify and report data mismatches. These data integrity checks enable design teams to resolve data differences quickly and easily before beginning physical verification, reducing the risk of schedule delays.