Skip to Main Content
white paper

Crossing the Chasm: Bringing SoC and Package Verification Together with Calibre 3DSTACK

Crossing the Chasm: Bringing SoC and Package Verification Together with Calibre 3DSTACK
For packaging technologies such as fan-out wafer-level packaging (FOWLP), the package design and verification process can be challenging. Because FOWLP manufacturing occurs at the “wafer level,” it incorporates mask generation, similar to the SoC manufacturing flow. Solid package design and verification flows must be in place so designers can ensure FOWLP manufacturability by the foundry or OSAT company. The Xpedition® Enterprise printed circuit board (PCB) platform provides a co-design and verification platform that utilizes both package design environments and SoC physical verification tools for FOWLP. Calibre 3DSTACK functionality extends Calibre die-level signoff verification to provide DRC and LVS checking of complete multi-die systems, including wafer-level packaging, at any process node, without breaking current tool flows or requiring new data formats.

Accurate verification of fan-out wafer-level packaging (FOWLP) designs requires integration of package design environments with system-on-chip (SoC) verification tools to ensure package manufacturability and performance

Wafer-level packaging (WLP) enables higher form factor and improved performance compared to sys­tem-on-chip (SoC) integrated circuit (IC) designs. While there are many wafer-level package design styles, fan-out wafer-level packaging (FOWLP) is a popular silicon-validated technology. However, for FOWLP designers to ensure an acceptable yield and performance, electronic design automation (EDA) companies, outsourced semiconductor assembly and test (OSATs), and foundries must collaborate to establish consistent, unified, automated design and physical verification flows. Uniting package design environments with SoC physical verification tools ensures the necessary co-design and verification platforms are in place. With the enhanced printed circuit board (PCB) design capabilities of the Xpedition Enterprise platform, and the expanded GDSII-based verification functionality of the Calibre platform combined with the Calibre 3DSTACK extension, designers can now apply Calibre die-level signoff DRC and LVS verification to a wide variety of 2.5D and 3D stacked die assemblies, including FOWLP, to ensure manufacturability and performance.

Share